A BICMOS IC fabrication process for fabricating both bipolar NPN and CMOS transistor structures recently in use at National Semiconductor Corporation, South Portland, Me. 04106 is summarized in TABLE I showing the overall BICMOS mask sequence. Further description of the BICMOS process mask sequence and sequence steps is also found in the Murray J. Robinson, Christopher C. Joyce, and Timwah Luk U.S. patent application Ser. No. 655,676 filed Feb. 14, 1991 for BIPOLAR TRANSISTOR STRUCTURE AND BICMOS IC FABRICATION PROCESS; the Robinson, Joyce, and Luk U.S. patent application Ser. No. 803,214 filed Dec. 6, 1991 for SCHOTTKY DIODE STRUCTURE AND FABRICATION PROCESS; the Donald J. Desbiens U.S. patent application Ser. No. 840,390 filed Feb. 24, 1992 for WAFER LEVEL RELIABILITY CONTACT TEST STRUCTURE; and the Robinson and Joyce U.S. patent application Ser. No. 905,772 filed Jun. 29, 1992 for SIMPLIFIED HIGH RELIABILITY GATE OXIDE PROCESS.
TABLE I ______________________________________ BICMOS WAFER FABRICATION MASK SEQUENCE Mask No. Mask Function ______________________________________ 1.0 N+ Buried Layer (N + BL) or NPN Buried Collector Layer (BCL) Mask 2.0 PMOS Retro NWELL Mask and NPN Retro SEC Mask 3.0 NMOS Retro PWELL Mask and Channel Stop (CHST) Mask 4.0 Isolation Oxide (ISOX) Mask 5.0 NPN Collector Sink (N + SINK) Definition Mask & ISOX Gettering Mask 6.0 CMOS Active Area Definition Mask (Active Mask) or Field Oxide (FOX) definition Mask & NPN Collector Base Surface Spacer (CBSS) Definition Mask 7.0 CMOS Active Strip Mask 8.0 Poly Gate (POLY) Definition Mask 9.0 NPN Base Definition Mask 10.0 2nd CVD Nitride Layer Etch Mask and NPN Collector Base & Emitter Contact Definition Mask 11.0 NPN Emitter Definition Mask & Collector Sink Contact Mask (Self-Aligned Transistor SAT Mask) 12.0 PMOS P + S/D Source/Drain Mask 13.0 NMOS N + S/D Source/Drain Mask 14.0 CMOS Contact Definition Mask 15.0 METAL 1 (M1) Definition Mask 16.0 VIA Mask (Inter Layer Dielectric Mask) 17.0 METAL 2 (M2) Definition Mask 18.0 Passivation Mask and Bond Pad Definition Mask ______________________________________
A buried collector layer BCL for bipolar NPN transistors is formed typically in a P type substrate P/SUB using the 1.0 BCL or N+BL mask, etch, and N type dopant material introduction sequence at the beginning of the BICMOS wafer fabrication process. The 1.0 N+BL mask is provided by a photoresist layer formed with openings defining the N+ buried layers and exposing an initial oxide layer over the substrate P/SUB. Relatively slow diffusing N type antimony atoms are implanted in the P type substrate through the 1.0 mask openings and initial oxide layer to an N+ concentration. The 1.0 mask is removed and a new photoresist layer is then deposited to form the 2.0 Retro NWELL mask.
The 2.0 retro NWELL mask sequence provides the Retro NWELL definition mask, etch, and N type impurity ion introduction sequence through NWELL openings for the CMOS/PMOS transistor structures. At the same time, it also provides a subemitter collector (SEC) region definition mask, etch, and N type impurity ion introduction sequence through SEC openings for the bipolar NPN transistor structures. By way of example, an SEC opening in the 2.0 Retro NWELL mask is formed with a horizontal area of approximately 10% and preferably in the range of 10% to 20% of the horizontal cross section area of the BCL. Relatively fast diffusing phosphorous atoms are implanted in the substrate P/SUB to an N+ concentration level through the 2.0 mask openings. Phosphorous atoms are used for the N+ concentration implant of the SEC and NWELL regions for faster up diffusion during subsequent annealing steps as hereafter described to provide retrograde concentrations extending into the subsequently deposited epitaxial layer EPI.
The 3.0 Retro PWELL mask, etch, and P type dopant material introduction sequence is used for defining and introducing the Retro PWELL regions for the CMOS/NMOS transistor structures and the channel stop regions CHST adjacent to the bipolar transistor structures. Boron atoms are implanted to a P+ concentration level in the PWELL and CHST regions through the 3.0 Retro PWELL mask openings. A single crystal epitaxial layer EPI of lightly doped N type silicon at an N- concentration is then deposited uniformly over the BICMOS IC structure in a blanket epitaxial deposition without a mask. The localized retrograde concentrations RETRO of P and N type material are initiated by diffusion upward from the Retro PWELL and Retro NWELL into the epitaxial layer EPI. An epitaxial oxide layer EPIOX and a first chemical vapor deposition CVD nitride layer CVDSIN are formed over the EPI.
Isolation oxide regions ISOX are established around the bipolar transistor structures using the 4.0 isolation oxide mask, etch and isolation oxide grow sequence. The NPN collector sink regions CS or N+SINK are defined by introducing an N+ concentration of phosphorous atoms using the 5.0 sink definition mask, etch and N type impurity ion introduction sequence. The 5.0 N+SINK definition mask is also formed with openings for introducing phosphorous atoms as a gettering agent in the isolation oxide regions ISOX. A second uniform CVD nitride layer is deposited in a blanket chemical vapor deposition across the BICMOS structure.
The 6.0 active area definition mask or Active Mask is formed with openings for etching the second CVD nitride layer CVDSIN around the active regions of the CMOS transistor structures. The openings in the 6.0 photoresist active mask expose the epitaxial layer EPI for growing field oxide regions FOX for framing and isolating the PMOS and NMOS transistor structures. Field oxide FOX is grown during the subsequent field oxide grow oxidation step.
At the same time the 6.0 Active Mask, etch and field oxide grow sequence also functions as the collector base surface spacer region CBSS definition mask, etch, and CBSS oxide grow sequence for the bipolar NPN transistor structures. The 6.0 photoresist active area definition mask functioning as a CBSS mask exposes the EPI surface area between the collector and base of bipolar transistors for the CBSS. In the subsequent field oxidation step, the collector base surface spacer region CBSS between the collector and base of bipolar transistors is formed from field oxide FOX rather than isolation oxide.
In the 7.0 active strip mask, etch, CMOS transistor voltage threshold (V.sub.T) adjust, and gate oxide grow sequence steps, the second CVD nitride layer is stripped except over the bipolar NPN transistor structures. Voltage threshold V.sub.T of CMOS transistors is adjusted in a P type material introduction step. In a series of subsequent steps sometimes referred to as the gate oxide loop or gate oxide sequence, the active areas of the CMOS transistor structures are opened to expose the epitaxial silicon and to grow a gate oxide layer GOX. These steps are described in detail in U.S. patent application Ser. No. 905,772 for SIMPLIFIED HIGH RELIABILITY GATE OXIDE PROCESS referenced above.
Gate material polysilicon (POLY) is subsequently deposited uniformly in one or two layers. The 8.0 poly gate definition mask and etch steps critically define the gates for CMOS transistors using a photoresist layer and photolithographic stepper sequence. The POLY layer is etched leaving behind the POLY gates over the gate oxide layer of CMOS transistors. No POLY is left over the bipolar NPN transistors. A thin oxide layer referred to as a sealing oxide or spacer oxide is grown over the POLY gates. A lightly doped source and drain N type dopant material introduction sequence such as an N- concentration phosphorus implant initiates preparation of the profile of source and drain regions of CMOS transistors.
The 9.0 NPN base definition mask, etch and introduction sequence is used for defining and introducing P type boron atoms for the base B of the bipolar NPN transistor structures. The base is implanted through the second CVD nitride layer CVDSIN which functions as a base implant screen. The 10.0 nitride etch mask provides a collector C, base B and emitter E contact definition mask using the second CVD nitride layer and forming a self-aligned transistor (SAT) CVD nitride mask over the bipolar NPN transistor structures. The epitaxial oxide layer EPIOX remains over the bipolar NPN transistor structures with the CVD nitride SAT mask openings defining the collector, base and emitter contacts.
The 11.0 NPN emitter definition and collector sink contact mask is constructed to utilize the underlying CVD nitride SAT mask over the bipolar NPN transistor structures. The emitter region E and collector sink contact region is implanted to an N+ concentration level with N type arsenic atoms. While previous annealing steps have begun development of the retrograde concentration upward through the epitaxial layer EPI from the PWELL, NWELL, and the SEC regions, the subsequent emitter annealing step following implant of the NPN emitter and collector sink contact regions fully develops most of the retrograde concentration profile of dopant atoms.
The 12.0 P+S/D source/drain mask, etch and P type dopant material introduction sequence is used for forming the P+ concentration source and drain regions of the PMOS transistor structures. The 13.0 N+S/D source/drain mask, etch and N type impurity ion introduction sequence for the NMOS transistor elements provides an N+ phosphorus implant over the previous lightly doped drain N- phosphorus implant in the source and drain regions. The combination of the N- and N+ phosphorous implants develops a profiled lightly doped drain for the NMOS transistor elements of the CMOS transistor pairs to reduce occurrence of "hot electrons".
Following the source/drain mask, etch and dopant material introduction sequences for the NMOS and PMOS transistor elements of the CMOS transistor structure, a blanket low temperature oxide layer LTO is deposited over the BICMOS structure. The 14.0 CMOS contact definition mask and etch sequence removes the LTO over the CMOS metal contact areas and over the bipolar transistor structure. The SAT CVD nitride mask on the bipolar transistor structures defines the bipolar transistor metal contact areas. Platinum is deposited and sintered forming platinum silicide over the metal contact areas. Unsilicided platinum is removed in a field etch. In subsequent mask steps the first metal layer is deposited and then selectively etched using the 15.0 Metal 1 or M1 definition mask and etch sequence for defining M1 metal contacts, followed by blanket deposition of an interlayer dielectric (ILD). The ILD is masked and etched using the 16.0 VIA mask to define the locations of interlayer contacts followed by blanket deposition of the second metal layer. The 17.0 Metal 2 or M2 definition mask and etch sequence defines the M2 metal contacts. A passivation layer such as a PECVD oxynitride layer is deposited over the BICMOS structure and the final 18.0 passivation mask and etch sequence cuts holes in the PECVD layer for bond pads.
A conventional lateral PNP transistor is typically fabricated in a bipolar or BICMOS process optimized for the fabrication of NPN transistors. An N type buried layer N+BL is formed in the semiconductor material substrate to underlie the PNP transistor. An N type epitaxial layer with an N type material concentration in the range of 2E16/cc is grown over the N type buried layer. A PNP base contact is provided by an N+SINK region extending through the N type epitaxial layer to the N+ buried layer. In typical lateral PNP transistor structures, the active base region is provided by the N type epitaxial layer over the N+ buried layer enhanced by N type material diffusing upward into the doped epitaxial layer.
The collector and emitter regions of the lateral PNP transistor structure are fabricated in the epitaxial layer using a P type mask, etch and introduction sequence from the bipolar or BICMOS fabrication process flow. Typically the NPN transistor base definition mask, etch and P type introduction sequence is utilized to form the emitter and collector regions of the lateral PNP transistor spaced apart by the PNP active base region of the N type epitaxial layer.
The conventional lateral PNP structure and fabrication process causes unnecessarily high parasitic junction capacitance across the junction between the N+ buried layer and P type regions. This problematic parasitic junction capacitance occurs at the junction of the N+ buried layer N+BL and non-active areas of the P type regions of the EPI. A second disadvantage of the conventional PNP transistor construction is that the base contact through the N+SINK region is made on the perimeter of an annular PNP collector region or on the outside or opposite side of the collector region from the emitter region. The base contact region must therefore be junction isolated from the collector region to avoid junction breakdown outside the PNP active transistor region. The lateral PNP transistor therefore requires significant spacing and is a relatively large geometrical structure on the integrated circuit.
A third disadvantage of the conventional PNP transistor structure and process is that the NPN base definition mask, etch and P type introduction sequence used to establish the emitter and collector regions of the PNP transistor also establishes the base width of the PNP transistor. In most bipolar and BICMOS fabrication processes, the NPN transistor base definition mask is not a critically controlled mask. Control over the base width of the PNP transistors and therefore control over the performance parameters of the PNP transistors is also limited.